SYNCHRONISM ACQUIRING DEVICE

摘要

PURPOSE:To reduce considerably influences of jitter and noise included in a bit synchronizing signal by using an average value of phase differences between the bit synchronizing signal and a sampling clock which are detected successively to control the phase of the sampling clock. CONSTITUTION:A bis synchronizing signal SY and a sampling clock D are supplied to a phase difference detector 14. A value corresponding to the pulse width of a phase difference signal E outputted from the phase difference detector 14 is integrated. An integral value N of an integrator 16 is supplied to a register 17. A value NR of the average phase difference outputted from the register 17 is supplied to a reset pulse generator 18, and a reset pulse C is generated at a time corresponding to the average phase difference value NR after the leading edge of the sampling clock D. This reset pulse resets a programmable counter 5 to delay the phase of the sampling clock by the time corresponding to the average phase difference value. Thus, the phase of the sampling clock is matched with the phase of the bit synchronizing signal of serial data A.