| 摘要 |
PURPOSE:To simultaneously read and write the number of bits according to the quantity of information and to increase or decrease the number of delay steps in inverse proportion to the quantity of information by providing an input information selecting section that selects arbitrarily input information to be written in a storage section from two or more information different in bit width and a column address controlling section that controls column address of the storage section. CONSTITUTION:The device is provided with a selector circuit 4 and a line address controlling circuit 8. Thereby, a line buffer of bit width (w) (1<=w<=n), the number of delay step (m)X(n/w) variable in bit width and the number of delay steps is constituted using a RAM 5 having (m) lines X (n) columns, and capacity (m)X(n) bits that can read and write information of n bits simultaneous ly. Consequently, in the case where subjects different in bit width of data such as a variable density picture image and a binary picture image, if the bit width is small, they can be used as a line buffer of many delay steps. Accordingly, many kinds of data can respond to minimum quantity of hardware, and espe cially, an area of exclusive possession can be held down to the minimum when the line buffer is made to LSI. |
