| 摘要 |
PURPOSE:To perform acquisition of synchronism efficiently even in circumstances where the reception electric field is varied by fading or the like, by using an S/N deciding circuit which discriminates the reception state to switch the mode of a digital PLL clock reproducing circuit in accordance with the reception state. CONSTITUTION:The first programmable frequency divider 8 and the second programmable frequency divider 9 are connected in series to a high-speed clock generator 5, and an S/N deciding circuit 10 which decides the S/N (the ratio of signal to noise) of an inputted digital signal (a) is provided. If the reception electric field is dropped by fading or the like to cause step out in a clock reproducing circuit and C/N is lower than 6dB, an S/N deciding circuit 6 judges S/N to be wrong, and the attack mode is set where the first programmable frequency divider 8 is fixed and the second programmable frequency divider 9 is controlled by the output of a racing counter 4. At this time, the synchronism acquisition time of the clock reproducing circuit is shortened, and the mode is switched to the protection mode when S/N is good. Thus, jitter is reduced, and the degradation in bit error rate due to jitter is reduced as much as possible. |
