| 摘要 |
PURPOSE:To enable the change in substrate potential as required by making the setting of well potential free by a method wherein a plurality of unit cells are arranged in matrix form, and in connecting these with wirings into a master slice IC, at least a part of these cells are made independent, and a well not fixed to any potential is provided. CONSTITUTION:A plurality of unit cells are arranged in matrix form and then connected into the master slice IC. Next, in forming a C-MOS circuit by using two cells of these cells, the following process is taken. That is, a P type well region 51 is formed in one cell, the N<+> type source and drain region 52 being provided therein, and polycrystalline Si regions 53 and 54 serving as the gate electrode being then formed thereon. The end of the region 51 is provided with a P<+> type region 55 to bias the region 51 and with a ground Al electrode 56 not connected to this region. The other cell is constructed in the same manner inspite of the different conductivity, and the change in substrate potential is facilitated by free setting of these well potentials. |
