| 摘要 |
PURPOSE:To speed up processing by stopping the reading and operation of two operands when decimal subtraction is applied and the two operands are superposed. CONSTITUTION:The output of a decimal subtraction instruction detecting part 1 connected to an instruction decode is applied to an OR circuit 4, an address register 2 and an address comparator 3 are connected to an address forming part and the output of the register 2 is applied to the circuit 4 through the comparator 3. The output of the circuit 4 is applied to an FF5 and an OR circuit 6, the output of the FF5 is applied to the circuit 6, the output of the circuit 6 is an operation control part 7 connected to an instruction decode and an address formation control part, and the output of the control part 7 to an operation executing part 8. When the starting address of the 1st operand stored in the register 2 coincides with the starting address of the 2nd operand and a decimal subtraction instruction is applied, address formation and the execution of the operation are stopped by the output from the circuit 4. |
