Transfer circuit for the transfer of coefficients

摘要

Coefficient records are to be supplied in rapid sequence alternately from one of two RAMs (RA, RB) to a transfer element (U) for digital signals, e.g. an adjustable level control, with a channel processor (KP). The coefficient records arrive from a processor (P), which can be controlled by a final control element, alternately to whichever RAM is not currently passing its stored data to the channel processor (KP). The speed at which the coefficients can be transferred is restricted by the fact that the coefficients have to be stored at scattered addresses in the RAMs. By using a transfer circuit (AR, DR, S1 to S8), in which the RAM addresses and the coefficients are temporarily stored in parallel using the same consecutive addresses provided by an address generator (AG), it is possible to achieve high-speed transfer of coefficients. <IMAGE>