| 摘要 |
PURPOSE:To execute a high-speed arithmetic processing by diving input data from a preceding stage with respect to plural segments in order, sequentially selecting and giving the respective output data to the subsequent state. CONSTITUTION:A pipeline arithmetic unit alternately inputs the data into segments S10 and S11 having the maximum delay time every one cycle of a clock input phi0, and alternately takes out the respective output data every one cycle of the clock input phi0. Moreover said unit can continuously process the data in the pipeline, and apparently the delay time can be halved. For example, even if the delay time of segments S0 and S2 is 30ns and that of segments S10 and S11 is 50ns, the latter is apparently shortened to 25ns. Therefore the frequency of the clock input phi0 can be set to a large value compensating the delay time 30ns of the segments S0 and S2 having a shorter delay time. |
