Self testing data processing system with system test master arbitration

摘要

The present invention relates to a self testing data processing system which includes a communications bus enabling communication between nonintelligent data processing circuits and a plurality of intelligent data processing circuits. The communications bus has connection slots, each connection slot having a unique electrically readable slot number. Each data processing circuit connects to the communications bus via one of the connection slots. Each data processing circuit has an identity memory which indicates whether or not that circuit can be a system test master. In addition, all intelligent data processing circuits include within their identity memory an indication of whether or not they have passed a circuit self test. Upon initial application of electric power or upon system reset, each intelligent data processing circuit performs a circuit self test and then sets the identity memory to indicate whether or not they have passed this self test. The intelligent data processing circuits then arbitrate to determine which circuit is to become the system test master. If an intelligent data processing circuit has failed its circuit self test or if it determines that an intelligent data processing circuit in a lower slot number has passed its own self test, then that intelligent data processing circuit defers system test control. The remaining intelligent data processing circuit, which has not deferred system test control, then takes control of the data processing system testing including testing of the nonintelligent data processing circuits.