| 摘要 |
PURPOSE:To attain the odd frequency division output of 50% duty by returning the inverted signal of the output of a shift register to an input and using an input signal as an input clock in case of the inverted signal and using the inverted signal as the input clock in case of the other level. CONSTITUTION:A frequency dividing counter is provided with an input terminal 4, a shift register 2 whose number of stages is (N+1)/2=3, a signal inverting circuit 3, a clock inverting circuit 1, and an output terminal 5. The circuit 1 operates exclusive OR between the output signal of the circuit 3 and the input signal A of 50% duty inputted to the terminal 4 and outputs the result as a clock B. the inverse of an output signal C and the clock B from the circuit 1 are inputted to a data terminal D and the clock terminal CK of the register 2, and the register 2 shifts the signal C by 3 stages in accordance with the leading of the clock B to output the output signal C from an output terminal Q. |
