| 摘要 |
<p>PURPOSE:To prevent a program content of an EPROM from being read to the outside of a LSI through a test of the EPROM and to facilitate the test by providing a read inhibition signal generating circuit, an I/O buffer circuit, and the 1st and 2nd gate circuits. CONSTITUTION:A read inhibition signal 21 is made active at the 3rd test mode and a gate circuit 6 applies the 3rd test mode signal to an I/O buffer circuit 4 and a gate circuit 5 closes an address signal 22 from a logic circuit 2. The I/O buffer circuit 4 is in the output mode in response to the 3rd test mode signal and a potential at an external address signal terminal 9 is fixed to a prescribed level potential from the gate circuit 5. An output from the EPROM 1 is closed by a gate circuit 8 at the same time and the level of the test terminal of the EPROM output is fixed to a prescribed value regardless of the output of the EPROM 1. Thus,the content of the EPROM read externally is prevented.</p> |
