| 摘要 |
In a data handling system having one or more processors, a cache memory associated with each processor and a main memory unit, each cache memory is divided into an equal number of portions, and the main memory is divided into a corresponding number of portions. A data transfer bus is provided between each group of cache memory portions and the corresponding portion of main memory such that each group of cache memory portions corresponds to only a portion of main memory. Each data transfer bus in independently controlled such that the rate of data transfers for the system as a whole is increased.
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