| 摘要 |
PURPOSE:To attain a logic action at a high speed and the power level reduction by using a simple static logic circuit and also performing the transmission of a carry through a single-stage clocked inverter circuit. CONSTITUTION:When half adder inputs (a) and (b) are kept at L levels, the signal (c) is set at an H level with the carry output CY1 set at an L level. When both inputs (a) and (b) are kept at H levels, the signal (d) and the output CY1 are set at L and H levels respectively. When either one of both inputs (a) and (b) is kept at an L level with the other kept at an H level, the signal (e) is set at an H level and a clocked inverter circuit 13 is active. Thus, the outputs CY1 is turned into CYO'. When half adder inputs (f) and (g) are kept at L levels, the signal (j) and the carry output CY2 are set at L and H levels respectively. When both input (f) and (g) are kept at H levels, the signal (i) and the output CY2 are set at H and L levels respectively. When one of both inputs (f) and (g) is kept at an H level with the other kept at an L level respectively, the signal (h) is set at an H level and a clocked inverter circuit 18 is active. Thus the output CY2 is turned into CY1'. In such a way, the static logic is formed with a simple circuit. This attains a logic action at a high speed and the power level reduction. |
