| 摘要 |
<p>19 A digital filter in the customary manner comprises a plurality of delay circuits, a plurality of multipliers and at least one summation device. The multipliers for fixed coefficients may be formed by means of adders and, if a pipeline structure is used, the summation device may also be formed by a plurality of adders. A result of this, only two different types of circuits are required, namely adders and delay circuits. In accordance with the invention it is proposed to initially integrate a plurality of adders and delay circuits in a regular structure without interconnections and to form the interconnections in a subsequent step after the filter structure has been defined. Suitably, the individual circuits are designed for one bit only and so-called cells are formed which each comprise a l-bit full adder and a plurality of registers, the cells being arranged in rows and columns. The connections of the elements within one or more cells are made by means of conductor tracks which all extend in one direction only and which intersect connecting lines which issue from the circuits.</p> |
