| 摘要 |
PURPOSE:To reduce the time required for re-locking by keeping a control voltage of a voltage controlled oscillator to a constant value when a reference signal input is lost for a short period. CONSTITUTION:A digital frequency divider 5 generates a forecast gate signal 23 covering the existing position of a reference signal input 1. A supervisory circuit 19 uses the reference signal input 1 and a gate signal 23 to output a reference signal input detection output 24 and a reference signal input undetected output 25. When the output 24 is not inputted for a predetermined time or over, a lock-on detector 20 outputs logic '0' of the output 26. A sample-and-hold control gate generator 21 generates a pulse of logic '1' from the output 25 up to the time constant. A sample-and-hold circuit 18 is operated as the sample mode when an output signal 28 is logic '0' and and as the hold mode when logic '1', that is, the circuit 18 holds an output voltage 8a and moment the logic '0' is changed into logic '1' and output a control voltage 8b. |
