发明名称 DATA PROCESSOR
摘要 PURPOSE:To set a substantial machine cycle time optionally without varying the timing of control over the operation of each hardware part by setting the number of basic clocks in a dummy cycle in a storage table and stopping the operation of every hardware part during the dummy cycle. CONSTITUTION:The dummy number (n) of basic clocks for a machine cycle clock is loaded in a clock control counter 3 while added to one machine cycle read out of the storage table 4. Then, the contents of the clock control counter 3 are checked by a machine cycle controller 2 at the timing 'TE' of the machine cycle clock 8; when its counted value is not zero, a dummy cycle signal 10 is made significant (low level) at the timing 'TE' and the dummy cycle is entered. While the dummy cycle signal 10 is significant, the operations of hardware except timing control are all stopped.
申请公布号 JPS6238918(A) 申请公布日期 1987.02.19
申请号 JP19850178562 申请日期 1985.08.15
申请人 MITSUBISHI ELECTRIC CORP 发明人 GOTO TOMOKO;ISHIDA TOMOKO
分类号 G06F11/22;G06F1/04;G06F1/08 主分类号 G06F11/22
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