| 摘要 |
<p>PURPOSE:To transmit the data of lots of bits in an asynchronizing system where high frequency noise hardly takes place while using a clock with conventional accuracy by using the synchronizing operation of an intermediate synchronizer so as to synchronize both clocks of a transmitter and a receiver on the way of transmission. CONSTITUTION:In case of 8-bit data transmission, each transmission/reception equipment interrupts the transmission at 4-bit transmission and the rest data is transmitted synchronously with the signal intermission of a synthesis signal TWAIT of communication wait request signals WAIT generated by each receiver. Since the clock of each transmission/reception equipment is corrected synchronously with the time of intermission of the synthesis communication wait request signal TWAIT, the clock error between the transmitter and the receiver is corrected at the end of transmission of the 1st half 4-bit. That is, when the clock period of the transmitter and receiver is both 2.tB and the clock of the receiver has the error of 2.tD per period to the clock of the transmitter, then the relation of tD<tB<(2.n) should be kept in a conventional system, where (n) is the transmission bit number including the parity bit, but in this system, n/2 is used in place of the said (n) and the accuracy of the clock is lowered by 1/2.</p> |
