发明名称 COORDINATE CONVERSION ARITHMETIC AND LOGIC UNIT
摘要 <p>PURPOSE:To simplify a constitution and to reduce cost by providing each two of multipliers and adders for a coordinate conversion. CONSTITUTION:At latching circuits 50-56, constants K00, K01, K10, K11, u0, and v0 are latched respectively. When switches SW1-SW5 are switched in the opposite shown in figure, the volume of K01.y(K1.y) is obtained at a multiplier 11(12) and that of K01.y+u0(K1.y+v0), that is, Zx(Zy) is obtained at an adder 21(22), being latched at a latching circuit 55(57). At the next, the switchers SW1-SW5 a returned to the position shown in figure and generating (x) coordinate position in order from a (x) coordinate generator 3, K00.x(K10.x) is added at the multiplier 11(12) and at the adder 21, the above value and Zx(Zy) latched at the latching circuit 55(57) are added, the value of u(v) shown in equations being calculated in order. Thereby, the constitution can be simplified and the cost is reduced.</p>
申请公布号 JPS6238982(A) 申请公布日期 1987.02.19
申请号 JP19850178596 申请日期 1985.08.15
申请人 FUJI ELECTRIC CO LTD 发明人 HORII HIROYUKI
分类号 G06F7/548;G06F17/14;G06F17/16;G06T3/00 主分类号 G06F7/548
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