SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To enable to reduce the wiring capacity of the titled device and to perform the readout operation of the device at higher speeds by a method wherein wirings, by which a first multiplexer and an output buffer are mutually connected, and wirings, by which a second multiplexer and the output buffer are mutually connected, are provided. CONSTITUTION:There are eight wires of wirings between the terminals Mn (n=1...8) of a multiplexer 3 and the terminals Bn(n=1...8) of an output buffer 4. The half of the terminals Mn of the multiplexer 3, which have been connected to 4 wires of wirings equal to the half of the eight wires of wirings and have been provided on the side of the output buffer 4, are disposed on the opposite side of a memory cell region 7 to the half terminals of the multiplexer 3. A part of a current distributor 2 inclusive of terminals Dn(n=1...4), which had been ever disposed at the positions of the half terminals of the multiplexer 3, is disposed on the opposite side of the memory cell region 7 to the terminals Dn and near the remaining part of the current distributor 2 inclusive of the terminal Mn (n=5...8) of the multiplexer 3. By this chip layout, the wiring between the terminal M1 of the multiplexer 3 and the terminal B1 of the output buffer 4, whose length had been ever the longest and whose wiring capacity had been also the largest, is shortened. As a result, a reduction of the wiring capacity of the semiconductor memory device is contrived and the readout operation thereof can be performed at higher speeds.