| 摘要 |
<p>PURPOSE:To decrease the pull-in time by applying phase correction of a reproduced clock only when a reception data is at a level of prescribed range so as to simplify the phase correction of the regenerated clock. CONSTITUTION:A counter 5 as a regenerated clock output circuit frequencydivides an output x1 of a pulse generating circuit 1 so as to obtain a regenerated clock x5. The phase correction of the clock x5 is controlled as shown in the following by a pulse x4. A circuit 2 generates a pulse x2 of a minute width at a point of time when an input in crosses a reference value Vc. A level measuring circuit 10 of a level discriminating circuit 3 detects the level of the reception signal in and when a detected output x10 is higher than the V1, an output x19 of a comparator 19 indicates a state ''1'' and when the x10 is lower than the level of a V2, an output x20 of a comparator 20 represents state ''1''. Then an AND circuit passes a pulse x2 when both the x19, x20 are at logical ''1'' and an x4 is obtained. A stable clock pulse is regenerated by using the x4 and clearing the counter 5 so as to correct the phase of an output x5.</p> |
