| 摘要 |
<p>PURPOSE:To set a substantial machine cycle optionally without varying the timing of control over the operation of each hardware part by setting the number of basic clocks in a dummy cycle to be added to a basic machine cycle and stopping the operation of every hardware part throughout the dummy cycle. CONSTITUTION:The dummy number (n) of basic clocks for generating a machine cycle clock in addition to one machine cycle generated with a model discrimination switch 4 is loaded in a clock control counter 3. Then, the contents of a clock control counter 3 are checked by a machine cycle controller 2 at the timing 'TE' of a machine cycle clock 6 and when its counted value is not zero, a dummy cycle signal 8 is signified (e.g. low level) at the end of the timing 'TE' and the dummy cycle is entered. While the dummy cycle signal 8 is significant, the all operations of hardware except timing control are stopped.</p> |
