| 摘要 |
PURPOSE:To inform a timing to which an abnormal operation is produced to the outside without providing any special circuit, by utilizing some of the address signals transmitted from a CPU as a trigger signal for the start of investigation of the abnormality when the abnormal operation occurs. CONSTITUTION:The highest order bit ADR15 of an address bus 12 consisting of address signal lines ADR0-15 of 16 bits is sent to a trigger signal buffer 23. Then the output of the buffer 23 can be taken to outside directly as a trigger signal. While the program of a working abnormality detecting part 20 is executed by a CPU 10. The control is shifted to a restoring part 22 by a trigger generating part 21 when the abnormality is detected. The part 22 delivers an instruction for the reset to an original program area. Here the highest order bit of the bus 12 is changed by the address signal transmitted from the CPU 10 for the fetching of the instruction. Thus the trigger signal is delivered from the buffer 23. |
