发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 PURPOSE:To improve timing follow-up performance by providing a voltage- controlled oscillating means which oscillates itself by a frequency source different from a timing frequency source for an input signal and corrects its self- oscillation frequency according to a control signal sent out of a phase control means. CONSTITUTION:The voltage-controlled oscillating means 7 is provided which has a phase error extracting means 5, oscillates itself at a baud rate frequency higher (or lower) than the reference frequency of the timing of, for example, the input signal and delays (or advances) the baud rate frequency by one time slot with the control signal sent out of the phase control means 6. The phase control means 6 integrates a shift value based on a phase error and sends out the control signal when the integrated value reaches one time slot of the baud rate frequency at which the voltage-controlled oscillating means 7 oscillates itself and the baud rate frequency of the voltage-controlled oscillating means 7 is corrected at intervals of one time slot to obtain synchronism with the timing of the input signal.
申请公布号 JPS6235717(A) 申请公布日期 1987.02.16
申请号 JP19850174764 申请日期 1985.08.08
申请人 FUJITSU LTD 发明人 KAKO TAKASHI;MIZUTANI YASUNAO
分类号 H03L7/08;H03L7/06;H03L7/093 主分类号 H03L7/08
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