| 摘要 |
PURPOSE:To improve the reliability of high-speed transmission by sampling a data signal on the transmission line by using the 3rd clock obtained by multiplying the 2nd received clock synchronously. CONSTITUTION:A frequency divider 9 divides the frequency of a tuning oscillator 12 by N and a transmission-side frequency divider 3 also divides the frequency of a fixed oscillator 2 by N. The phase difference between those two divided frequencies is detected by a phase comparator 6 and outputs at the output 14 of the phase comparator 6 as pulse width. The high frequency component is cut by an LPF 7 and an integration circuit 8 integrates the phase difference to obtain a voltage value. The tuning oscillator 12 varies the oscillation frequency according to the output 15 of the integration circuit 8 so that the output 15 of the integration circuit 8 is '0' eventually. A serial communication interface 5 samples data on a data line with the obtained demodulated clock 16. |
