| 摘要 |
a CPU for performing a selecting control of a channel; an address decoder for decoding the address signal to select a channel and generating a chip select signal ; an OR gate for controlling a write timing in response to the decoded chip select signal and the channel select data write control signal of the CPU; a data ratch for ratching the output channel select data of the CPU under the write timing control of the OR gate; a TV tuner for selecting a channel in response to the output data of the data ratch; a data reading section for supplying the channel select completion data of the TV tuner to the CPU adjusting into the data read timing of the CPU; and a memory for restoring the selected channel under the control of the CPU. |
