DIELECTRIC BREAKDOWN PREVENTION TECHNIQUE

摘要

A technique for preventing thin gate dielectric layer (16) breakdown by shorting the gate (18) to the silicon substrate (12) by means of a metal layer (24) which will eventually form silicided gate (26) and source/drain (28) interconnections. A sidewall spacer (22) around each gate (18) is necessary to prevent shorting during and after the silicidation process. Suitable metals for the thin metal shorting layer (24) include chemical vapor deposited (CVD) tungsten, titanium, tantalum, molybdenum and platinum. This technique prevents the need for special metal layer deposition or removal steps commonly used in the art to prevent catastrophic gate dielectric (16) breakdown due to high charge build-up on the gate (18).