| 摘要 |
<p>A memory circuit (10) has a plurality of bit line pairs (203, 204) and intersecting word lines (218-220) with a memory cell (205-207) located at each such intersection. A column address selects the bit line (203, 204) which is to be accessed and a row address selects the word line (218-220) which is enabled. In response to being selected, a bit line (203-204) is coupled to a data line (216, 217). In response to a column address transition, all of the bit lines (203, 204) are decoupled from the data lines (216, 217) while bit lines (203, 204) are precharged. In response to a row address transition, the word lines (218-220) are disabled while the bit lines (203, 204) are equilibrated.</p> |
