| 摘要 |
PURPOSE:To easily detect asynchronization with a simple circuit by inputting an output lock and an input clock of a PLL circuit to an OR circuit and detecting a fault of the PLL circuit on the basis of the output of said OR circuit. CONSTITUTION:When the output clock f0 of the PLL circuit is synchronized (locked state) with its input clock fi, fixed phase relation is formed between the input clock fi and the output clock f0. However when both the clocks fi, f0 are asynchronized, the output clock f0 travels independently and the superposition of the low timing of the input clock fi to that of the output clock f0 will be generated without fail. If both the input clock fi and output clock f0 are negative polarity clock, an output signal may be obtained by finding out the OR of both the clock pulses in the asynchronous state. Consequently, the generation of asynchronization in the PLL circuit can be decided by the output of the OR circuit 6. |
