| 摘要 |
PURPOSE:To shorten the time needed for processing data on the wiring design, etc. by performing the data processing with hardware after providing cells in an array and with total or partial asynchronization with a clock. CONSTITUTION:Cells 401 forming an array part 303 are connected to the cells in four directions adjacent to each other via bidirectional data transfer lines 402 excluding the cells at both ends of vertical and horizontal directions respectively. A control part 302 receives the data needed for wiring processing from a host computer and sends it to the part 303 together with a control signal, etc. Then the part 302 receives the data again after the necessary processing is over. In other words, the signals are transmitted in wave forms to four directions from a cell at the starting point by the control signal sent from the part 302 in a cell action mode or a clock asynchronous mode. Thus the data transfer direction is decided. Then a route is decided via a data transfer line decided previously from a terminal point. Thus the signal is transmitted asynchronously between cells by the hardware. This accelerates the transmission of signals and shortens the time for wiring design, etc. |
