发明名称 PIPELINED MULTIPLYING CIRCUIT
摘要 PURPOSE:To speed up processing and improve economy while maintaining high precision by comparing the result of subtraction of a partial product group part to be discarded from the product of the modulo 3 residue of an input operand with the modulo residue of a carry look-ahead adder. CONSTITUTION:A modulo 3 residue product generating circuit 18 generates the product of the modulo 3 residue of a multiplicand register 15 and the modulo 3 residue of a multiplier register 16. A modulo 3 residue product generating circuit 19 for a partial product generates the product of the modulo 3 residue of a part to be displayed as to the partial product of a multiplicand and a multiplier. A modulo subtracting circuit 20 subtracts the modulo 3 residue output of part of the partial product group to be discarded obtained by the circuit 19 from the output of the circuit 18. A comparator 26 compares the output of the circuit 20 with the output of the modulo 3 residue generating circuit 26 of the carry look- ahead adder 24. Then, a multiplication error is detected from the comparison result.
申请公布号 JPS60144827(A) 申请公布日期 1985.07.31
申请号 JP19840000753 申请日期 1984.01.09
申请人 NIPPON DENKI KK 发明人 YAGIHASHI TOSHIO
分类号 G06F7/38;G06F7/00;G06F7/483;G06F7/499;G06F7/508;G06F7/527;G06F7/533;G06F11/10 主分类号 G06F7/38
代理机构 代理人
主权项
地址