| 摘要 |
There are provided memory cell arrays MA1 to MA4 each of which includes a predetermined number of redundant memory cell rows and a predetermined number of redundant memory cell columns, and which are caused to partially operate by a block selecting signal BS. Replacement address programming circuits RAP1 to RAP4 of the number smaller than the number of the redundant memory cell rows, are provided. Each of the replacement address programming circuits stores the row address of a defective memory cell(s) existing in the memory cell arrays MA1-MA4, and outputs a redundant row selection discriminating signal RSJ1-RSJ4 of an activated level when a row address signal XA designates the stored row address. Further, selection circuits RS1 to RS8 are provided for selecting one of the redundant row selection discriminating signals RSJ1 to RSJ4 and selecting a corresponding redundant memory row. The number of redundant column address programming circuits included in redundant column selection circuits RYS1 and RYS2 is made smaller than the number of the redundant memory cell columns.
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