| 摘要 |
<p>A parallel multiplicator including adder circuits based on Booth's algorithm is disclosed. All of the adders of a plurality of rows are constructed based on the carry save system. When the negative partial-product signal is input, the "2's complement" generating signals CB0 to CB3 for the LSB of the negative partial-product signal are input to the bit adder in the lowest order row which corresponds to the LSB of the negative partial-product signal. </p> |
