| 摘要 |
PURPOSE:To convert simply an input data with a prescribed length serial or parallel signal into a serial or parallel output data by providing a bit length selection circuit changing the period of a load pulse LPi to a generating section of a timing signal. CONSTITUTION:The load pulse LPi to specify the bit length is outputted from the timing generating section 20 and fed to a data conversion section 50. The data conversion section 50 is provided with a terminal 51 to which the bit length is selected externally and an external load pulse LPo is fed. Thus, the load pulse LPi outputted from the timing signal generating section 20 functions as an internal load pulse. A serial data SDi is inputted to a terminal 52 and a parallel data PDi is inputted to a terminal P (composing of plural terminal groups). In using selection pulses SL1, SL2, the load pulse LPi having a prescribed period is formed. Thus, is changing the logic constitution of a selection circuit 42, the load pulse LPi having an optional period is formed. |
