| 摘要 |
PURPOSE:To make it unnecessary to leave an especially large margin on design to improve the read time by generating the timing of the driving signal of a sense amplifier from the delay characteristic due to a memory device itself. CONSTITUTION:The sense amplifier consists of P-channel MOSFETs P11 and P12 and N-channel MOSFETs N5 and N6. When a precharge signal phiP is in the high level, transistors TRs P1-P4 and P15 are turned on to precharge column lines D1, D'1, D2, and D'2 and a signal phiD1 to the high level. When the signal phiP goes to the low level, a selected row line X1 rises, and an end part X10 of the row line goes to the high level after the delay due to the resistance of the row line and the capacity, and a RAM cell discharges one of pairs of column lines D1 and D'1 and column lines D2 and D'2, and the signal phiD1 is discharged by either of MOSFETs N12 and N13. An inverter I sets a discharge signal phiD to the high level, and the sense amplifier is set to the active state, and the column line D2 goes to the low level quickly, thus completing read. |
