发明名称 FAULT ANALYSIS SYSTEM
摘要 PURPOSE:To automate easily the processing of analysis by inputting a fault into an analyzer while being divided into the logic state and the physical state, analyzing the former with the programmed logic of its own algorithm of a stored program and analyzing the latter with a conventional analyzer. CONSTITUTION:The operating state of the stored program is collected by a collector 2. On the other hand, the stored program of a system during execution stores the addresses of a memory damp information memory device 3 corresponding to prescribed names D1, D2.... Then a physical state converter 4 extracts a prescribed faulty state and a name (item name), arranges them into a data string 5, which is given dividedly to a logic state converter 6 and a physical state analyzer 10 to proceed the processing. As the result of the logic state analyzer 8, 'Level B is under execution' is displayed on a display device 9 as to the logic state, and for example, print-out (list output) is performed. The data string inputted to the analyzer 10 is analyzed by the hardware processing such as a logic operation circuit and the physical state as to the fault is outputted on a display device 11.
申请公布号 JPS6223267(A) 申请公布日期 1987.01.31
申请号 JP19850162640 申请日期 1985.07.23
申请人 FUJITSU LTD 发明人 ICHIKAWA MINORU;OSAWA JIRO;HASEGAWA SEIICHI
分类号 G06F11/22;H04M3/22;H04Q1/22 主分类号 G06F11/22
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