| 摘要 |
In a data processing system having a plurality of peripheral devices (16) and a main memory (12), a direct memory access controller controls the transfer of data between the main memory (12) and the peripheral devices (16). The controller includes a local memory (38) connected to the peripheral devices (16) for storing data writtren to and read from the peripheral devices (16), a sequencer (30) for controlling the transfer of data between the main memory (12) and the local memory (38), a local address register (34) connected to the sequencer (30) for providing the local memory address for memory operations of the local memory (38), a system address register (32) connected to the sequencer (30) for providing the main memory address for memory operations of the main memory (12) and a data register (56, 58) for holding data transferred between the main memory (12) and the local memory (38). The sequencer (30) includes means for generating control signals for the main memory (12), the local memory (38) and the data register (56, 58) in control cycles such that, in a single control cycle, a first word is read out of the register (56, 58) and a second word is written into the register (56, 58), whereby n words can be transferred in n+1 control cycles. |
