SWITCHED CAPACITOR MULTIPLICATION CIRCUIT

摘要

A switched-capacitor multiplier circuit for multiplying an information signal x(t) by a bipolar carrier signal d(t) consisting of a distributed multiplier circuit with which the bipolar carrier signal is normally associated. To reduce offset voltages in the output signal caused by the operational amplifiers used and caused as a result of clock feed-through, it is not the bipolar carrier signal itself, but a full-wave rectified version thereof that is associated with the distributed multiplier circuit. The output signal of the multiplier circuit is applied to an auxiliary multiplier circuit multiplying it by +1 or -1 dependent on the instantaneous polarity of the bipolar carrier signal d(t). The offset voltage is thereby transposed to a frequency which is at least equal to the fundamental frequency of the carrier signal so that, if desired, it can be suppressed with the aid of a suitably chosen low-pass filter without the desired signal being affected thereby.