| 摘要 |
PURPOSE:To evade the change of an output voltage and unstableness of an output by using an average value of the non-inverted output voltage and the inverted output voltage of a differential logic circuit as the gate reference voltage. CONSTITUTION:The differential logic circuit is provided with FETs 1 and 2, and an input signal Vin is supplied to the gate of the FET 1, and the reference voltage is given to the gate of the FET 2. An average voltage value V is given in accordance with V=(V1+V2) where V1 and V2 are the non-inverted output voltage and the inverted output voltage of the differential logic circuit respectively. Voltages V1 and V2 are constant independently of the variance of the supply voltage, and the voltage V is gate biased to stabilize the reference voltage. Thus, the change of the output voltage and unstableness of the output are evaded. |
