| 摘要 |
PURPOSE:To improve bus use efficiency and facilitate increasing the number of stages of a pipeline by using each bus effectively by time division and constituting the multistage pipeline with a small number of busses. CONSTITUTION:When data A1 is transferred from the external through a bus 13, it is inputted to a processor P1 synchronously with a clock. Data B1 of the operation result of preceding inputted data is outputted to the bus 13 by the next clock. Data B1 is inputted to a processor P2 of the succeeding stage by the next clock, and an operation result C1 of preceding inputted data is outputted by the next clock. That is, the input period of the processor P1, the output period of the processor P1, the input period of the processor P2, and the output period of the processor P2 are determined in time division to flow data on the bus 13. |
