发明名称 |
Bifurcated method and apparatus for floating point addition with decreased latency time |
摘要 |
Apparatus for decreasing the latency time associated with floating point addition and subtraction in a computer, using a novel bifurcated, pre-normalization/post-normalization approach that distinguishes between differences of floating point exponents.
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申请公布号 |
US4639887(A) |
申请公布日期 |
1987.01.27 |
申请号 |
US19840583531 |
申请日期 |
1984.02.24 |
申请人 |
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE UNITED STATES DEPARTMENT OF ENERGY |
发明人 |
FARMWALD, PAUL M. |
分类号 |
G06F7/485;G06F7/00;G06F7/50;G06F7/507;G06F7/76;(IPC1-7):G06F7/50 |
主分类号 |
G06F7/485 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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