Non-volatile semiconductor memory device having vertical transistors and fabrication method therefor

摘要

A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral length of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.