| 摘要 |
PURPOSE:To enhance a withstand voltage by forming a vertical groove on an N-type Si substrate at the positions of the prescribed interval of an active region periphery of a vertical semiconductor device, coating a polysilicon, and diffusing an N-type impurity in the substrate around the polysilicon and the groove. CONSTITUTION:An SiO2 film 5d is formed on an N-type layer 2 on an N<+> type Si substrate 1, a hole is selectively opened to form a P<+> type layer 3, and a gate oxide film 5a is adhered. Then, the film 5d is selectively opened, reactively ion-etched to form a vertical groove 11, and polysilicons 6a, 6b are selectively formed. A P<+> type is diffused in the layer 6a, a P-channel 4 is formed by ion implanting and heat treating, and P<+> type layers 4a, 4b are formed around the groove 11. Then, SiO2 films 5b, 5c and N<+> type source 8, source electrode 9 and drain electrode 10 are formed as prescribed to complete it. According to this configuration, narrow and deep field limiting ring is formed of the groove 11 and the layer 4b to obtain a high-withstand vertical semiconductor device. |
