发明名称
摘要 PURPOSE:To shorten the latency time of data transmission and reception to and from a phase controller and to allowing a terminal itself to have an opportunity of outputting data, by stopping operation at the time received data is edited and stord, and outputting the stored data when its output condition is satisfied. CONSTITUTION:A receiving circuit 11 judges the 1st byte of received data and when the medium indication is a medium A, the 2nd and succeeding bytes are stored successively in a print buffer 15; and an indication of printing to the medium A is sent to a print head 19 through a print driver 18 and the operation is completed. When the 1st byte of the data indicates another medium, the 2nd and succeeding bytes are stored in a medium storage area of an RAM14 for print data storage and the operation is completed. When the data indicates discharge, the medium A is discharged from a conveyance part 21 through a conveyance control part 16 by the indication of a CPU12, which receives the report of the completion of conveyance from the control part 16 to store data in a buffer 15 other than the data of a medium A of the RAM14, allowing the data to be printed out.
申请公布号 JPS623456(B2) 申请公布日期 1987.01.24
申请号 JP19820055501 申请日期 1982.04.05
申请人 OKI ELECTRIC IND CO LTD 发明人 ABE TADAO
分类号 G06F3/12;B41J11/48;B41J29/38;G06K15/00;G06K15/16 主分类号 G06F3/12
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