| 摘要 |
PURPOSE:To prevent occurrence of poor pattern position alignment and to implement highly accurate alignment, by forming a wafer aligning target by the same processes for an element isolating region, and thereafter forming at least an aligning target part by self-aligning etching with respect to the element isolating region. CONSTITUTION:On a silicon substrate 1, an SiO2 film 2 and an Si3N4 film 3 are deposited on the entire surface. A resist pattern 4 is formed only on an element part and a target part. With the resist pattern 4 as a mask, the Si3N4 film 3 and the SiO2 film 2 are etched away. Thereafter, with the Si3N4 film 3 as a mask, an Si exposed part is selectively oxidized, and an SiO2 film 5 is formed. The Si3N4 film 3 and the SiO2 film 2 are removed. Then, a resist film 6 is formed only on the element part B. An Si exposed part 7 in the target part A under-goes anisotropic dry etching, and a groove is formed. Thereafter, the resist film 6 is removed. |
