发明名称 SHIELDED TYPE SEMICONDUCTOR DEVICE
摘要 PURPOSE:To reduce a soft-error rate by alpha-rays by forming a p-n junction into a semiconductor substrate region, in which charge pairs are generated by the incidence of alpha-rays, utilizing the contact potential difference of the p-n junction or applying reverse bias voltage and forming a shielding layer. CONSTITUTION:An n-type semiconductor layer 13 is shaped on the side further lower than a p-type region 12, and an inflow to an n<+> buried layer 11 of charged generated by alpha-rays is prevented. That is, charges by alpha-rays are not generated in the p-type diffusion layer region 12 when the p-type diffusion layer 12 is not more than several dozen mum thick, thus slightly flowing currents into the n<+> buried layer 11. Contact potential difference with the formation of a p-n junction is generated on the interface between the p-type region 12 and the n-type region 13, electrons in charges generated by alpha-particles are attracted to the n-type region 13, and holes are drawn to the p-type region 12 biassed at a negative value, thus extremely reducing the inflow of charges to the n<+> buried layer 11.
申请公布号 JPS6212150(A) 申请公布日期 1987.01.21
申请号 JP19850150168 申请日期 1985.07.10
申请人 HITACHI LTD 发明人 NISHIOKA TAIJO;JINRIKI HIROSHI;MUKAI KIICHIRO
分类号 H01L21/8229;G11C29/00;G11C29/04;H01L27/10;H01L27/102 主分类号 H01L21/8229
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