| 摘要 |
PURPOSE:To obtain a vertical MOSFET with a low ON resistance by providing a high-concentration impurity region in the surface of a common drain region before the formation of a source region. CONSTITUTION:An SiO2 mask 17 is applied to a P-type Si substrate 1 and an N-type channel 2 is formed by ion implantation 12 of P and wet oxidization. An aperture is drilled in an SiO2 film 17' to form an N<+> type layer 13. SiO2 is selectively left on the surface and the surface is covered with a gate oxide film 6 and a thick film part 19 is formed and a gate electrode 5 of polycrystalline Si 5' is formed. An N<-> type drain 3, which is effective to obtain a high dielectric strength, is formed between the adjacent gate electrodes 5 and an N<-> type layer 4' is formed around the N<+> type layer 13 by ion implantation 14 of B. Then CVD SiO2 16 is applied and an aperture is drilled and B ions are diffused to form an N-type source 4. Then PSG 10 is applied and an aperture is drilled after the annealing in an N2 atmosphere and an Al source electrode 7 and a gate lead-out electrode are provided and an Au electrode 8 is applied to the back plane of the substrate to complete the device. By providing the high concentration layer 13 in the surface of a common drain (substrate) before the formation of the source 4 as described above, practically the same effect as the expansion of a current path can be obtained so that a vertical FET with a low ON resistance and a high dielectric strength can be obtained. |
