| 摘要 |
A CPU data path portion having an ALU, an adjuster unit, a shifter unit and a shift register unit is disclosed. The CPU is capable of selectively forming the sum or difference of a first BCD operand and a second BCD operand by arithmetically combining the operands with the ALU to form binary results, the results dependent upon the arithmetic operation selected and adjusting the results with the adjuster unit into BCD, the adjustment also dependent upon the arithmetic operation selected. The CPU is further capable of selectively converting an operand from binary to BCD format or from BCD to binary format by iteratively shifting the operand between the shifter unit and the shift register unit and correcting the operand with the ALU, the direction of the shift and the ALU correction dependent upon the conversion selected.
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