发明名称 COMPLEMENTARY MOS LATCH CIRCUIT
摘要 PURPOSE:To reduce two MOS transistors and to make reduction of cell area possible by connecting the gates of MOS transistors to a control terminal to make simultaneous control of on/off, and making an inverter of a control input line unnecessary. CONSTITUTION:When a control signal inputted to a control terminal 17 is low level, N-type MOS transistors Q15, Q17 become off simultaneously, and P-type MOS transistors Q12, Q14 become on simultaneously. Accordingly, the first tristate 11 connected to input side becomes the state of high impedance when looked from an output side, and the second tristate 12 connected to an output side becomes equivalent to the inverter. Therefore, the signal output outputted to an output terminal is kept in a fixed state irrespective of signal input inputted to an input terminal. When the control signal is high level, the first tristate becomes equivalent to the invertor and the second tristate 12 becomes high impedance. Accordingly, the signal input is transmitted to signal output as it is.
申请公布号 JPS6210924(A) 申请公布日期 1987.01.19
申请号 JP19850148911 申请日期 1985.07.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OKABAYASHI ICHIRO
分类号 H03K19/0185;H03K3/356;H03K19/00;H03K19/094;H03K19/0948 主分类号 H03K19/0185
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