| 摘要 |
<p>A digital integrated circuit is described, comprising a logic circuit (11) and a linear feedback shift register (12) for applying a pseudo-random sequence of test patterns to the inputs of the logic circuit. The number of stages in the register is greater than the number of inputs to the logic circuit. As a result, a test pattern which would otherwise be missing (e.g. all zeros) is produced as part of a longer test pattern, avoiding the need for loading the missing pattern separately into the register.</p> |
