| 摘要 |
<p>Disclosed is an apparatus for synchronizing a first signal wilh a second signal comprising a plurality of delay means D<Sub>i</Sub> as i goes from 1 to N, where N is an integer, each delay means D<Sub>i</Sub> having an input I<Sub>i</Sub> and a delay output O<Sub>i</Sub> for delaying a signal received at the respective input I, by an increment 8t of time in supplying the delayed signal at the respective delay output O<Sub>i</Sub>.</p><p>The first delay means D, of the plurality of delay means is connected to receive the first signal at its input I<Sub>1</Sub>. Each of the other delay means D,, for i equal to 2 to N, are connected in series such that the respective input I<Sub>i</Sub> is connected to receive the delay output O<Sub>i-1</Sub> of the preceding delay means D<Sub>i-1</Sub>.</p><p>A plurality of latch means L<Sub>i</Sub>, as i goes from 1 to N, are connected to be clocked by the second signal. Each of the latch means L<Sub>i</Sub> latches the signal at the delay output O<Sub>i</Sub> respectively for each of the delay means D<Sub>i</Sub>, in response to the second signal and supplies the latched signal at a respective latch output Q<Sub>i</Sub>.</p><p>Output logic means, responsive to at least a subset of the plurality of delay outputs O<Sub>i</Sub> and plurality of latch outputs Q<Sub>i</Sub>, for supplying essentially a phase-shifted copy of the first aignal synchronized with the second signal is provided.</p> |
