| 摘要 |
Clocked control signals are applied from a source to the input of delay means having a plurality of successive signal takeoff points, with the delay between successive ones of said takeoff points being the same (e.g., a period at the signal clocking frequency, fCL). An "and" gate is provided with a plurality of inputs equal in number to the plurality of takeoff points. Each takeoff point is linked by a signal path to a respectively different one of the "and" gate inputs. A succession of two-input "or" gates is provided, with one input of each "or" gate coupled to receive the output of the "and" gate. The last of the succession of "or" gates is coupled to a control signal output terminal. The output of each of the remainder of said succession is coupled via a respectively different one of a plurality of similar delay devices to the other input of the next succeeding one of said succession of "or" gates. Each of the delay devices imparts a delay equal to a period at fCL. The other input of the first of said succession of "or" gates is coupled to directly receive the control signal source output.
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